Embedded Flash Memory for Embedded Systems: Technology, Design for Sub-systems, and Innovations by Hideto Hidaka

Author:Hideto Hidaka
Language: eng
Format: epub
Publisher: Springer International Publishing, Cham

the high suspend-resume rate affects write timing because the charge-discharge of HV nets at each transition, plus the recovery time needed by the algorithm, must be added to the physical time of the suspended and resumed write operation

Read-while-write (RWW) memories are a more sophisticated solution for an NVM runtime update. In RWW architecture, array blocks are organized as partitions that can be independently read or written. Typically, partitions are independent from both a logical and a physical point of view; this means that address and data paths are duplicated as are the HV switches required to handle write voltages. The main reason for that is to limit the area of the devices area involved in HV endurance stress, to reduce the leakage current at high temperature sunk by internal HV supplies (generally internal charge pumps ), and to avoid cross-disturbance .

Therefore, from an application perspective, RWW memory is suitable for a clear differentiation path because array partitions are quite well confined from a physical-implementation point of view. Code memory inherits the role of EPROM, as matter of monolithic content that gets written in a well-defined time window in the life of the product, usually when the application is not running. Data memory becomes a flash 1T-NOR array with a high degree of specialization to emulate the word alterability of EEPROM (which, in most of the cases, becomes a replacement in embedded systems of the external EEPROM component).

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